1. Field of the Invention
The present invention relates to a method for synchronizing a clock, generated with the assistance of a counter, to a reference clock that is supplied via a reference line.
2. Description of the Prior Art
FIG. 1 illustrates a specific application of a synchronization circuit SYN in a central clock supply of a telecommunications switching center that is synchronized by an external reference frequency f.sub.E according to the master/slave principle. The central clock supply is composed of a first, central clock generator CCG1 and of a second, central clock generator CCG2, whereby, in normal operation of the central clock supply, the first, central clock generator CCG1 generates a first clock f.sub.1 from the external reference clock f.sub.E via a first phase-locked loop PLL1 and via a first counter C1, this first clock f.sub.1 being through-connected by way of a switch s1a to the output of a clock supply and synchronizing the switching center as the exchange clock.
While this is occurring, the second, central clock generator CCG2 forms a second clock f.sub.2 of the same frequency via a second phase-locked loop PLL2 and via a second counter C2, the second clock f.sub.2, however, being through-connected to the output of the central clock supply as an exchange clock by way of a second switch s2a only in a backup sense (given outage of the first, central clock generator or for routine test purposes). When, therefore, the switch s1a is closed, then the switch s2a is opened and vice-versa. A switch s1p and a switch s2p have the same relationship to one another. During normal operation of the central clock supply, the switch s2p is closed and the switch s1p is opened, whereas the switch s2p is opened and the switch s1p is closed in the backup case given a change of the normallyactive, first central clock generator.
Since, in the backup case, the first clock f.sub.1 is replaced by the second clock f.sub.2 as the exchange clock, it is necessary in order to avoid the phase skip that the second clock also coincides with the first clock, that represents the reference clock here, with respect to the phase relation at all times.
It is known to meet the requirement with the assistance of a synchronization circuit SYN that, for example, registers each trailing edge of the reference clock and that resets a counter with the respective, following leading edge of a counting clock, as a result whereof the clock generated by this counter is constantly synchronized to the reference clock. Supplying the synchronization circuit with the reference clock thereby occurs via a reference line L.sub.R.
When pulses can arise given a sudden outage of the reference clock or due to undesired over-couplings onto the reference line appear on the reference line, for example, then the trailing edges thereof likewise lead to a synchronization and, in the specific example of FIG. 1, effect a lasting, irreversible phase skip of the exchange clock given a subsequent change of the active, central clock generator.